1. Field of the Invention
The present invention relates in general to pipelined asynchronous logic circuits that can be employed to implement programmable logic circuits such as Field Programmable Gate Arrays (FPGAs) without the use of a global or system clock. Logic blocks formed from fine grain pipelined logic elements, each including only a small amount of logic, can be used to implement any desired logic function and communicate with one another using an asynchronous hand shaking technique.
2. Description of the Background Art
Most existing FPGA architectures rely on the use of a global or system clock to synchronize operation of the various logic gates in the array. These clocked systems suffer from a number of inherent drawbacks. For example, pipelined logic circuits are typically employed in FPGAs in which groups of logic blocks or elements are connected in sequence to carry out a desired complex logic operation. It is often necessary to change the depth (i.e. number of logic blocks in the sequence) of one or more pipelines to change the FPGA's programming. Changing local pipeline depths in a clocked system can require global retiming of the entire system since the delays imposed by the pipeline vary with its depth. Adding high-speed retiming hardware support to a clocked FPGA incurs a significant register overhead. In addition, clocked FPGAs are prone to delay variation induced errors that can result from temperature and supply voltage fluctuations, as well as from physical imperfections of the circuit chip, for example. Further, clocked FPGAs are not efficient from an energy usage standpoint because all of the logic gates in the array are enabled by each clock pulse, even when many of the gates are not required for a given computation.
The use of asynchronous circuits in programmable logic arrays and the like can overcome the foregoing drawbacks associated with clocked FPGAs. However, while the first FPGA was introduced by Xilinx in 1985 and the first asynchronous microprocessor was designed at Caltech in 1989, very little work has been performed in the last two decades to combine asynchronous and programmable circuit technology. Moreover, what work has been done in this area has not been particularly successful and has been based largely on programmable clocked circuits. These FPGAs are limited to low-throughput logic applications because their asynchronous pipeline stages are either built up from gate-level programmable cells or use bundled-data pipelines. One example of a fabricated asynchronous FPGA chip using bundled-data pipelines operated at an un-encouraging maximum of 20 MHz in a 0.35 μm CMOS process. Another drawback of previously proposed asynchronous FPGAs is that they could not use generic synchronous FPGA place and route tools. For example, the CAD tools for one asynchronous architecture known as the Montage FPGA architecture needed to enforce the isochronic fork delay assumption required for safe prototyping of QDI circuits. A need therefore remains for an asynchronous FPGA architecture that provides enhanced performance over conventional clocked FPGAs.